SPI vs I2C: speed or pins
Almost every chip you bolt onto a microcontroller — a sensor, a flash, a display, a real-time clock — talks over one of two buses: SPI or I2C. They solve the same problem, connecting a host to peripherals on the same board, and the choice between them reduces to a single trade-off. SPI buys speed with wires. I2C buys wires with speed. Everything below is a footnote to that sentence.
Same job, two wiring philosophies
SPI uses three shared lines — clock (SCLK), data out (MOSI) and data in (MISO) — plus a dedicated chip-select line to every device. There are no addresses: the master picks a peripheral by pulling its select line low. Add a device, add a wire. The lines are push-pull, so edges are sharp and the clock can run fast.
I2C uses exactly two lines — clock (SCL) and data (SDA) — no matter how many devices hang off them. There is no per-device wire; instead every device answers to a 7-bit address. The lines are open-drain and pulled high by resistors, so any device (or the master) can hold them low, which is what makes the shared, acknowledged, multi-master bus possible — and what limits its speed.
Figure 1 — The whole difference in one picture. SPI: 3 shared lines + 1 select per device, push-pull. I2C: 2 lines for everything, open-drain with pull-ups, devices picked by address.
Why reach for SPI
Speed. This is the headline. Push-pull drivers and the absence of any per-byte addressing or acknowledgment mean an SPI byte is just eight clock edges — nothing else on the wire. Clocks of tens of megahertz are routine (50 MHz and beyond), against I2C’s 100 kHz / 400 kHz / 1 MHz tiers. SPI is also full-duplex: it shifts a byte out on MOSI while shifting one in on MISO, simultaneously.
Simple, deterministic timing. No addresses, no acknowledgments, no clock stretching to wait on. The select line frames the transfer; you clock bits. That predictability is why throughput-bound peripherals demand SPI: serial flash, SD cards, TFT displays, high-rate ADCs and DACs, audio codecs.
The cost is in the wiring: a chip-select line per device, four wires minimum, and no acknowledgment — SPI never tells you a device actually heard you.
Figure 2 — One byte on each bus. SPI spends 8 clocks and nothing else. I2C pays a START, an address, and an ACK after every byte — overhead that, with the open-drain rise time, caps how fast it can go.
When I2C is the right call
Pins. Two wires, full stop — whether you hang two devices or twenty off them. When a board carries a crowd of slow peripherals — EEPROM, RTC, temperature and humidity sensors, IO expanders, fuel gauges, the configuration port of a bigger chip — and the MCU is short on GPIO, I2C wins outright. SPI would demand a chip-select for each; I2C just adds an address.
Built-in handshaking. Every device acknowledges every byte, so the master knows its write landed — a free “are you there?” that SPI lacks. Addressing, multi-master arbitration and clock stretching give the bus real flow control.
The cost is speed and a little bookkeeping: the open-drain rise time (pull-up resistor against total bus capacitance) caps the clock, and fixed device addresses can collide — two parts at 0x48 need an address-select pin or a bus mux.
The rule
| SPI | I2C | |
|---|---|---|
| Wires | 3 shared + 1 select/device | 2 (SCL, SDA) |
| Pick a device by | chip-select line | 7/10-bit address |
| Duplex | full (MOSI + MISO) | half |
| Drive | push-pull | open-drain + pull-ups |
| Typical clock | tens of MHz (50+) | 100 k – 3.4 M |
| Acknowledge | none | ACK/NACK per byte |
| Multi-master | awkward | native |
| Per-byte overhead | ~0 (just 8 clocks) | START + address + ACKs |
| Scales by adding | wires (GPIO) | addresses (can collide) |
The decision almost writes itself: need bandwidth → SPI; need to fit many slow parts on few pins → I2C. A display, a flash, an SD card or a fast converter goes on SPI because nothing else keeps up. A drawer of sensors, an EEPROM and an RTC go on I2C because two wires carry them all.
Figure 3 — Sort each peripheral, not the whole board. High-throughput parts land in SPI; crowds of low-rate parts land in I2C. Many MCUs run both buses at once for exactly this reason.
Field notes
- Count the chip-selects before committing to SPI. N devices means N select lines; run out of GPIO and you are adding a decoder or shift register just to pick chips.
- An I2C device that won’t ACK is usually not dead. Check the pull-ups (value against bus capacitance) and address conflicts before you suspect the part.
- Mind I2C bus capacitance. Long traces and many devices slow the edges; drop to 100 kHz or add a bus buffer/accelerator rather than fighting rounded rise times.
- CPOL/CPHA mismatch is the number-one SPI “it doesn’t work.” Both ends must agree on clock polarity and phase — confirm the mode before debugging anything else.
- Pick per peripheral, not per board. Need speed and few pins? That is why QSPI and dual-SPI exist for flash, and why many sensors offer both buses — wire each part to the bus that fits it.