Integrate a dBc/Hz profile into RMS phase error and jitter — the clock-tree sanity check.

From dBc/Hz to femtoseconds

Phase noise L(f) is single-sideband power density relative to the carrier. The total phase error integrates both sidebands:

φ_{rms}^{2} = 2 \int_{f_{1}}^{f_{2}} 1 0^{L (f) /10} df

and the jitter is just that phase error divided by the angular carrier rate:

t_{jitter} = \frac{φ _{rms}}{2 π f _{c}}

The integration is done segment by segment assuming L is linear between your points on a log-frequency axis (each segment is a power law — exactly how vendors' own tools do it). Two rules of thumb: the area is usually dominated by the flat far-out floor, so extending f₂ matters more than the close-in detail; and a 156.25 MHz SerDes reference at 100 fs RMS is healthy, while the same profile on a 10 MHz clock would be 16× more phase error simply because the carrier is slower.

Phase Noise → Jitter Converter

From dBc/Hz to femtoseconds