Thermal Via Array (θ)
Thermal resistance of a plated via and of N vias in parallel under a hot part.
Pushing heat through the board
A hot SMD part on the top layer often has to dump its heat into a plane on an inner or the bottom layer. Bare FR-4 is a poor conductor (~0.3 W/mK), so you punch a field of plated vias under the pad — each is a little copper pipe for heat. One via's thermal resistance is:
where L is the board thickness, k the conductivity (copper ≈ 385
W/mK) and A the copper cross-section — for a plated barrel that's the copper
annulus, π(r_o² − r_i²). An unfilled barrel's hole adds almost nothing
(air); filling it with thermal epoxy helps a little, solder more, and a copper-filled via
makes the whole cylinder conduct.
Because the vias are thermally in parallel, the array resistance is one via's divided by the count — so the lever is how many you fit under the pad. A typical 0.3 mm via is ~190 K/W alone but a 4×4 array drops to ~12 K/W. Combine this with the junction-temperature chain to size the whole thermal path.