CAN Bit Timing Calculator
Prescaler, TSEG1, TSEG2 and sample point for a target CAN bitrate — with register values.
How a CAN bit is built
Each CAN bit is divided into an integer number of time quanta (TQ). One TQ is the CAN clock divided by the baud-rate prescaler:
The bit has three parts: a fixed 1-TQ SYNC segment, then TSEG1 (propagation + phase-1), then TSEG2 (phase-2). The receiver samples the bus at the boundary between TSEG1 and TSEG2 — the sample point:
For 500 kbit/s and 1 Mbit/s, CiA recommends a sample point around 87.5%; slower buses with long cables often use 75–80%. The SJW (resynchronization jump width) is how many TQ the controller may stretch or shrink a bit to stay in sync — keep it ≤ TSEG2. Every node on the bus must agree on bitrate and sample point, so match them across the network.