CIC Filter Calculator
Gain, bit growth, passband droop and alias rejection for a cascaded integrator-comb filter.
The multiplier-free decimator
A CIC filter is the workhorse first stage of nearly every FPGA decimator: N
integrators running at the high rate, a rate change of R, then N comb
sections at the low rate — no multipliers at all, just adders and registers.
Its DC gain and the register width you must carry both grow with the rate change:
That bit growth is the number-one CIC gotcha — undersize the accumulators and they overflow silently. The frequency response is a cascade of sincs, so the passband isn't flat: it droops toward the band edge by
evaluated at the band-edge frequency (referenced to the input rate). The same sincs put deep nulls at multiples of the output rate, which is what gives the alias/image rejection — but the worst-case rejection sits at the inner edge of the first folding band, and it sets how much downstream filtering you still need. In practice a CIC is almost always followed by a short compensation FIR that flattens the droop and sharpens the transition. Pair this with the FIR designer for that stage.