PWM Frequency & Resolution
PWM frequency, duty resolution and timer registers (ARR / PSC / CCR) from the timer clock.
How a timer makes PWM
The timer counts up from 0 to at the prescaled clock, then reloads — that ramp sets the PWM period. The output is high while the counter is below the compare value , so:
The catch is resolution: duty can only step in units of one count, so the number of distinct duty levels is , giving
There's a hard trade-off — for a fixed clock, a higher PWM frequency means a smaller ARR and fewer bits of duty resolution. Want both? Raise the timer clock or pick a timer with a wider counter.
Frequently asked questions
How do I calculate PWM frequency from a timer?
PWM frequency = timer clock ÷ ((PSC+1) × (ARR+1)). The prescaler PSC divides the clock, and the counter period ARR+1 sets how many ticks make up one PWM cycle.
What is PWM resolution in bits?
The number of distinct duty-cycle steps equals ARR+1, so the resolution in bits is log2(ARR+1). For example ARR=999 gives 1000 steps ≈ 9.97 bits.
Why does a higher PWM frequency reduce resolution?
For a fixed timer clock, raising the PWM frequency forces a smaller ARR, which means fewer counter steps and therefore fewer bits of duty resolution. To keep both high, increase the timer clock or use a wider (e.g. 32-bit) timer.
How do I set a specific duty cycle?
Load the compare register CCR with round(duty × (ARR+1)). The output stays high while the counter is below CCR, so the duty cycle equals CCR ÷ (ARR+1).